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january 2004 dav digital audio/speaker data manua l sles068a tm
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband interface interface.ti.com digital control www.ti.com/digitalcontrol logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security telephony www.ti.com/telephony video & imaging www.ti.com/video wireless www.ti.com/wireless mailing address: texas instruments post office box 655303, dallas, texas 75265 copyright ? 2004, texas instruments incorporated
contents iii february 2003?revised january 2004 sles068a contents section page 1 introduction 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 features 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 functional block diagram 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 terminal assignments 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 ordering information 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 terminal functions 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 architecture overview 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 clock and serial data interface 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1 normal-speed, double-speed, and quad-speed selection 7 . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.2 clock master/slave mode (m_s) 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.3 clock master mode 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.4 clock slave mode 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.5 pll filter 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.6 dclk 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.7 serial data interface 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 reset, power down, and status 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 reset?reset 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 power down?pdn 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3 general status registers 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.4 error status register 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 signal processing 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 volume control 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.2 mute 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.3 automute 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.4 individual channel mute 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.5 de-emphasis filter 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 pulse width modulator (pwm) 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.1 clipping indicator 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.2 error recovery 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.3 individual channel error recovery 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.4 pwm dc-offset correction 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.5 interchannel delay 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.6 pwm/h-bridge and discrete h-bridge driver interface 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 i 2 c serial control interface 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.1 single-byte write 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.2 multiple-byte write 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.3 single-byte read 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.4 multiple-byte read 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 serial control interface register definitions 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 general status register (0x00) 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 error status register (0x01) 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 system control register 0 (0x02) 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 system control register 1 (0x03) 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 error recovery register (0x04) 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 automute delay register (0x05) 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 dc-offset control registers (0x06?0x0b) 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
list of illustrations iv february 2003?revised january 2004 sles068a 3.8 interchannel delay registers (0x0c?0x11) 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 individual channel mute register (0x19) 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 system procedures for initialization, changing data rates, and switching between master and slave modes 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 system initialization 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 data sample rate 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 changing between master and slave modes 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 specifications 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 absolute maximum ratings over operating temperature ranges 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 recommended operating conditions 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 electrical characteristics over recommended operating conditions 37 . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 static digital specifications over recommended operating conditions 37 . . . . . . . . . . . . . . 5.3.2 digital interpolation filter and pwm modulator over recommended operating conditions (fs = 48 khz) 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.3 TAS5026A/tas5110 system performance measured at the speaker terminals over recommended operating conditions (fs = 48 khz) 38 . . . . . . . . . . . . . . . . 5.4 switching characteristics 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.1 command sequence timing 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.2 serial audio port 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.3 serial control port?i 2 c operation 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 application information 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 serial audio interface clock master and slave interface configuration 48 . . . . . . . . . . . . . . . . . . . . . . . . 6.1.1 slave configuration 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.2 master configuration 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 mechanical data 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . appendix a?volume table 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . list of illustrations figure title page 2?1 crystal circuit 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?2 external pll loop filter 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?3 i 2 s 64-fs format 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?4 i 2 s 48-fs format 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?5 left-justified 64-fs format 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?6 left-justified 48-fs format 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?7 right-justified 64-fs format 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?8 right-justified 48-fs format 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?9 dsp format 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?10 attenuation curve 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?11 de-emphasis filter characteristics 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?12 pwm outputs and h-bridge driven in btl configuration 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?13 typical i 2 c sequence 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?14 single-byte write transfer 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?15 multiple-byte write transfer 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?16 single-byte read 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
list of tables v february 2003?revised january 2004 sles068a 2?17 multiple-byte read 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?1 reset during system initialization 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?2 extending the i 2 c write interval following low-to-high transition of reset terminal 32 . . . . . . . . . . . . . . . . . 4?3 changing the data sample rate using the dbspd terminal 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?4 changing the data sample rate using the i 2 c33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?5 changing the data sample rate with an unstable mclk_in using the dbspd terminal 34 . . . . . . . . . . . . . . 4?6 changing the data sample rate with an unstable mclk_in using the i 2 c35 . . . . . . . . . . . . . . . . . . . . . . . . . . 4?7 changing between master and slave clock modes 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?1 reset timing 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?2 power-down and power-up timing?reset preceding pdn 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?3 power-down and power-up timing?reset following pdn 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?4 error recovery timing 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?5 mute timing 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?6 right-justified, i 2 s, left-justified serial-protocol timing 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?7 right, left, and i 2 s serial-mode timing requirement 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?8 serial audio ports master-mode timing 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?9 dsp serial-port timing 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?10 dsp serial-port expanded timing 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?11 dsp absolute timing 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?12 scl and sda timing 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?13 start and stop conditions timing 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?1 typical TAS5026A application 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?2 TAS5026A serial audio port?slave-mode connection diagram 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?3 TAS5026A serial audio port?master-mode connection diagram 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . list of tables table title page 2?1 normal-speed, double-speed, and quad-speed operation 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?2 master and slave clock modes 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?3 lrclk and mclk_in rates 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?4 dclk 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?5 supported word lengths 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?6 device outputs during reset 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?7 values set during reset 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?8 device outputs during power down 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?9 volume register 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?10 de-emphasis filter characteristics 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?11 device outputs during error recovery 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?1 i 2 c register map 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?2 general status register (read only) 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?3 error status register 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?4 system control register 0 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?5 system control register 1 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?6 error recovery register 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
list of tables vi february 2003?revised january 2004 sles068a 3?7 automute delay register 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?8 dc-offset control registers 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?9 six interchannel delay registers 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?10 individual channel mute register 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
introduction 1 sles068a?february 2003?revised january 2004 TAS5026A 1 introduction the TAS5026A is an innovative, cost-effective, high-performance 24-bit six-channel digital pulse-width modulator (pwm) based on equibit ? technology. combined with a ti purepath digital ? audio amplifier power stage, these devices use noise-shaping and sophisticated error correction algorithms to achieve high power efficiency and high-performance digital audio reproduction. the TAS5026A is designed to drive up to six digital power devices to provide six channels of digital audio amplification. the digital power devices can be six conventional monolithic power stages (such as t as5110) or six discrete differential power stages using gate drivers and mosfets. the TAS5026A has six independent volume controls and mute. the device operates in ad mode. this all-digital audio system contains only two analog components in the signal chain?an lc low-pass filter at each speaker terminal and can provide up to 96-db snr at the speaker terminals. the TAS5026A has a wide variety of serial input options including right justified (16, 20, or 24 bit), i2s (16, 20, or 24 bit) left justified, or dsp (16-bit) data formats. the device is fully compatible with aes standard sampling rates of 44.1 khz, 48 khz, 88.2 khz, 96 khz, 176.4 khz, and 192 khz including de-emphasis for 44.1-khz and 48-khz sample rates. the TAS5026A was designed for home theater applications such as dvd minicomponent systems, home theater in a box (htib), dvd receiver, a/v receiver, or tv sets. 1.1 features ? ti purepath digital audio amplifier ? high quality audio ? 96-db snr ? <0.1% thd+n ? six-channel volume control ? patented soft volume ? patented soft mute ? 16-, 20-, or 24-bit input data ? sampling rates: 44.1 khz, 48 khz, 88.2 khz, 96 khz, 176.4 khz, and 192 khz ? supports master and slave modes ? 3.3-v power supply operation ? economical 64-pin tqfp package ? digital de-emphasis: 32 khz, 44.1 khz, and 48 khz ? clock oscillator circuit for master modes ? low jitter internal pll ? soft volume and mute update equibit and purepath digital are trademarks of texas instruments. other trademarks are the property of their respective owners.
introduction 2 sles068a?february 2003?revised january 2004 TAS5026A 1.2 functional block diagram pwm ch. output control avdd_pll avss_pll vrega_cap vregb_cap vregc_cap dvdd_rcl dvss_rcl dvdd_pwm dvss_pwm power supply pll_flt_out pll_flt_ret sclk lrclk mclkout sdin1 sdin2 sdin3 mclk_in xtal_out xtal_in dbspd sda scl cso pwm_ap_1 valid_1 pwm_ap_2 valid_2 pwm ap_3 valid_3 pwm_ap_4 valid_4 pwm_ap_5 valid_5 pwm_ap_6 valid_6 pwm am_3 pwm_am_1 pwm_am_2 pwm_am_4 pwm_am_5 pwm_am_6 clock, pll and serial data i/f pdn reset mute clip err_rcvry serial control i/f reset, pwr dwn and status auto mute de-emphasis soft volume error recovery soft mute clip detect signal processing pwm section pwm ch. pwm ch. pwm ch. pwm ch. pwm ch. m_s dm_sel1 dm_sel2
introduction 3 sles068a?february 2003?revised january 2004 TAS5026A 1.3 terminal assignments 17 dvdd_rcl dvss_rcl nc dvdd_pwm dvss_pwm pwm_ap_4 pwm_am_4 valid_4 pwm_ap_5 pwm_am_5 valid_5 pwm_ap_6 pwm_am_6 valid_6 nc nc 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 nc mclk_in avdd_pll pll_flt_out pll_flt_ret avss_pll nc dvss1 rst err_rcvry mute pdn sda scl cs0 dvss1 18 19 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 pag package (top view) dbspd clip sdin1 sdin2 sdin3 mclk_out sclk lrclk dvdd dvss1 nc dem_sel2 dem_sel1 m_s dvss1 dvss1 avdd_osc xtl_in xtl_out avss_osc dvss pwm_ap_1 pwm_am_1 valid_1 pwm_ap_2 pwm_am_2 valid_2 pwm_ap_3 pwm_am_3 valid_3 nc nc 20
introduction 4 sles068a?february 2003?revised january 2004 TAS5026A 1.4 ordering information texas instruments t as audio solutions 5026a pag device number package type available options package t a plastic 64-pin tqfp (pag) 0 c to 70 c TAS5026Apag 1.5 terminal functions terminal function ? description name no. function ? description avdd_osc 64 p analog power supply for internal oscillator cells avdd_pll 3 p 3.3-v analog power supply for pll avss_osc 61 o analog ground for internal oscillator cells avss_pll 6 p analog ground for pll clip 18 o digital clipping indicator, active low cs0 15 i i 2 c device address select. this is an active high pin. dbspd 17 i sample rate is double speed (88.2 khz or 96 khz), active high dm_sel1 29 i de-emphasis select bit 1 (0 = none, 01 = 32 khz, 10 = 44.1 khz dm_sel2 28 i de-emphasis select bit 2, 10 = 48 khz, 11 = undefined (none) dvdd_pwm 45 p 3.3-v digital power supply for pwm dvdd_rcl 48 p 3.3-v digital power supply for re-clocker dvdd 25 p 3.3-v digital power supply for digital core and most of i/o buffers dvss 60 i voltage regulator enable, active low dvss_pwm 44 p digital ground for pwm dvss_rcl 47 p digital ground for re-clocker dvss1 8, 26, 31, 32 p digital ground for digital core and most of i/o buffers err_rcvry 10 i error recovery, active low lrclk 24 i/o serial audio data left/right clock (sampling rate clock) (input when m_s = 0; output when m_s = 1) m_s 30 i master/slave mode input signal (master = 1, slave = 0) mclk_in 2 i mclk input, slave mode mclk_out 22 o mclk output buffered system clock output m_s = 1; otherwise set to 0 mute 11 i mute input signal, active low ? i = input; o = output; i/o = input/output; p = power
introduction 5 sles068a?february 2003?revised january 2004 TAS5026A terminal function ? description name no. function ? description nc 1, 7, 27, 33, 34, 36, 49, 50 ? no connection pdn 12 i power down. this signal is active low. pll_flt_out 4 i pll external filter pll_flt_ret 5 i pll external filter pwm_am_1 58 o pwm 1 output (differential -); {positive h-bridge side} pwm_am_2 55 o pwm 2 output (differential -); {positive h-bridge side} pwm_am_3 52 o pwm 3 output (differential -); {positive h-bridge side} pwm_am_4 42 o pwm 4 output (differential -); {positive h-bridge side} pwm_am_5 39 o pwm 5 output (differential -); {positive h-bridge side} pwm_am_6 36 o pwm 6 output (differential -); {positive h-bridge side} pwm_ap_1 59 o pwm 1 output (differential +); {positive h-bridge side} pwm_ap_2 56 o pwm 2 output (differential +); {positive h-bridge side} pwm_ap_3 53 o pwm 3 output (differential +); {positive h-bridge side} pwm_ap_4 43 o pwm 4 output (differential +); {positive h-bridge side} pwm_ap_5 40 o pwm 5 output (differential +); {positive h-bridge side} pwm_ap_6 37 o pwm 6 output (differential +); {positive h-bridge side} rst 9 i system reset input. this signal is an active low. scl 14 i i2c clock signal sclk 23 i/o serial audio data clock (master mode = output, slave mode = input) sda 13 i/o i2c data signal sdin1 19 i serial audio data 1 input sdin2 20 i serial audio data 2 input sdin3 21 i serial audio data 3 input valid_1 57 o output indicating validity of pwm outputs, channel 1, active high valid_2 54 o output indicating validity of pwm outputs, channel 2, active high valid_3 51 o output indicating validity of pwm outputs, channel 3, active high valid_4 41 o output indicating validity of pwm outputs, channel 4, active high valid_5 38 o output indicating validity of pwm outputs, channel 5, active high valid_6 35 o output indicating validity of pwm outputs, channel 6, active high xtl_in 63 i crystal or ttl level clock input xtl_out 62 o crystal output (not for external usage) ? i = input; o = output; i/o = input/output; p = power
introduction 6 sles068a?february 2003?revised january 2004 TAS5026A
architecture overview 7 sles068a?february 2003?revised january 2004 TAS5026A 2 architecture overview the TAS5026A is composed of six functional elements: ? clock, pll, and serial data interface (i 2 s) ? reset/power-down circuitry ? serial control interface (i 2 c) ? signal processing unit ? pulse-width modulator (pwm) ? power supply 2.1 clock and serial data interface the TAS5026A clock and serial data interface contain an input serial data slave and the clock master/ slave interface. the serial data slave interface receives information from a digital source such as a dsp, s/pdif receiver, analog-to-digital converter (adc), digital audio processor (dap), or other serial bus master. the serial data interface has three serial data inputs that can accept up to six channels of data at data sample rates of 32 khz, 44.1 khz, 48 khz, 88.2 khz, 96 khz, 176.4 khz, and 192 khz. the serial data interfaces support left justified and right justified for 16-, 20-, and 24-bits. in addition, the serial data interface supports the dsp protocol for 16 bits and the i 2 s protocol for 24 bits. the TAS5026A can function as a receiver or a generator for the mclk_in (master clock), sclk (shift clock), and lrclk (left/right clock) signals that control the flow of data on the three serial data interfaces. the TAS5026A is a clock master when it generates these clocks and is a clock slave when it receives these clocks. the TAS5026A is a synchronous design that relies upon the master clock to provide a reference clock for all of the device operations and communication via the i 2 c. when operating as a slave, this reference clock is mclk_in. when operating as a master, the reference clock is either a ttl clock input to xtal_in or a crystal attached across xtal_in and xtal_out. the clock and serial data interface has two control parameters: data sample rate and clock master or slave. 2.1.1 normal-speed, double-speed, and quad-speed selection the data sample rate is selected through a terminal (dbspd) or the serial control register 0 (x02). the data sample rate control sets the frequencies of the sclk and lrclk in clock slave mode and the output frequencies of sclk and lrclk in clock master mode. there are three data rates: normal speed, double speed, and quad speed. normal-speed mode supports data rates of 32 khz, 44.1 khz, and 48 khz. normal speed is supported in the master and slave modes. double-speed mode is used to support sampling rates of 88.2 khz and 96 khz. double speed is supported in master and slave modes. quad-speed mode is used to support sampling rates of 176.4 khz and 192 khz. the pwm is placed in normal speed by setting the dbspd terminal low or by setting the normal mode bits in the system control register 0 (x02) through the serial control interface. the pwm is placed in double speed mode by setting the dbspd terminal high or by setting the double speed bits in the system control register. quad-speed mode is auto detected supported in slave mode and invoked using the i 2 c serial control interface in master mode. in slave mode, if the TAS5026A is not in double speed mode, quad-speed mode is automatically detected when mclk_in is 128fs. in master mode, the pwm is placed in quad-speed mode by setting the quad-speed bit in the system control register through the serial control interface. if the master clock is well behaved during the frequency transition (the high or low clock periods are not less than 20 ns), then a simple speed selection is simply performed by setting the dbspd terminal or the serial control register. when the sample rate is changed, the TAS5026A temporarily suspends processing, places the pwm outputs in a hard mute (pwm p outputs low; pwm m outputs high, and all valid signals low), resets all internal processes, and suspends all i 2 c operations. the TAS5026A then performs a partial re-initialization and noiselessly restarts the pwm output. the TAS5026A preserves all control register settings throughout this sequence. if desired, the sample rate change can be performed while mute is active to provide a completely silent transition. the timing of this control sequence is shown in section 4.
architecture overview 8 sles068a?february 2003?revised january 2004 TAS5026A if the master clock input can encounter a high clock or low clock period of less than 20 ns while the data rates are changing, then reset should be applied during this time there are two recommended control procedures for this case, depending upon whether the dbspd terminal or the serial control interface is used. these control sequences are shown in section 4. table 2?1. normal-speed, double-speed, and quad-speed operation quad-speed control register bit dbspd terminal or control register bit mode speed selection 0 0 master or slave normal speed 0 1 master or slave double speed 1 0 master or slave quad speed 0 0 slave quad speed if mclk_in = 128 fs 1 1 master or slave error 2.1.2 clock master/slave mode (m_s) clock master and slave mode can be invoked using the m_s (master slave) terminal. this terminal specifies the default mode that is set immediately following a device reset. the serial data interface setting permits the clock generation mode to be changed during normal operation. the transition to master mode occurs: ? following a reset when m_s terminal has a logic high applied the transition to slave mode occurs: ? following a reset when m_s terminal has a logic low applied 2.1.3 clock master mode when m_s = 1 following a reset, the TAS5026A provides the master clock, sclk, and lrclk to the rest of the system. in the master mode, the TAS5026A outputs the audio system clocks mclk_out, sclk, and lrclk. the TAS5026A device generates these clocks plus its internal clocks from the internal phase-locked loop (pll). the reference clock for the pll can be provided by either an external clock source (attached to xtal_in) or a crystal (connected across terminals xtal_in and xtal_out). the external source attached to mclk_in is 256 times (128 in quad mode) the data sample rate (fs). the sclk frequency is 64 times the data sample rate and the sclk frequency of 48 times the data sample rate is not supported in the master mode. the lrclk frequency is the data sample rate. 2.1.3.1 crystal type and circuit in clock master mode the t as5026a can derive the mclkout , sclk, and lrclk from a crystal. in this case, the TAS5026A uses a parallel-mode fundamental-mode crystal. this crystal is connected to the TAS5026A as shown in figure 2?1.
architecture overview 9 sles068a?february 2003?revised january 2004 TAS5026A xo TAS5026A osc macro r d c 1 xi c 2 avss r d = drive level control resistor ? crystal vendor specified c l = crystal load capacitance (capacitance of circuitry between the two terminals of the crystal) c l = (c 1 x c 2 )/(c 1 + c 2 ) + c s (where c s = board stray capacitance ~ 3 pf) example: vendor recommended c l = 18 pf, c s = 3 pf c 1 = c 2 = 2 x (18?3) = 30 pf figure 2?1. crystal circuit 2.1.4 clock slave mode in the slave mode (m_s = 0), the master clock, lrclk, and sclk are inputs to the TAS5026A. the master clock is supplied through the mclk_in terminal. as in the master mode, the TAS5026A device develops its internal timing from the internal phase-locked loop (pll). the reference clock for the pll is provided by the input to the mclk_in terminal. this input is at a frequency of 256 times (128 in quad mode) the input data rate. the sclk frequency is 48 or 64 times the data sample rate. the lrclk frequency is the data sample rate. the TAS5026A does not require any specific phase relationship between srclk and mclk_in, but there must be synchronization. the TAS5026A monitors the relationship between mclk, sclk and lrclk. the TAS5026A detects if any of the three clocks are absent, if the lrclk rate changes more than 10 mclk cycles since the last device reset or clock error, or if the mclk frequency is changing substantially with respect to the pll frequency. when a clock error is detected, the TAS5026A performs a clock error management sequence. the clock error management sequence temporarily suspends processing, places the pwm outputs in a hard mute (pwm_p outputs are low; pwm_m outputs are high, and all valid signals are low), resets all internal processes, sets the volumes to mute, and suspends all i 2 c operations. when the error condition is corrected, the TAS5026A exits the clock error sequence by performing a partial re-initialization, noiselessly restarting the pwm output, and ramping the volume up to the level specified in the volume control registers. this sequence is performed over a 60-ms interval. the TAS5026A preserves all control register settings that were set prior to the clock interruption. if a clock error occurs while the err_rcvry terminal is asserted (low), the TAS5026A performs the error management sequence up to the unmute sequence. in this case, the volume remains at full attenuation with the pwm output at a 50% duty cycle. the volume can be restored from this latched mute state by triggering a mute/unmute sequence by asserting and releasing mute either by using the terminal, the system control register x01 d4, or the individual channel mute register d5?d0. alternatively, the TAS5026A can be prevented from entering the latched mute state following a clock error when the err_rcvry terminal or the error recovery i 2 c command (register x03 bit d2) is active by writing x7f to the individual error recovery register (x04) and a x84 to x1f (a feature enable register).
architecture overview 10 sles068a?february 2003?revised january 2004 TAS5026A table 2?2. master and slave clock modes description m_s dbspd xtl_in (mhz) ? mclk_in (mhz) ? sclk (mhz) lrclk (khz) ? mclk_out (mhz) # internal pll, master, normal speed 1 0 8.192 - 2.048 32 8.192 internal pll, master, normal speed 1 0 11.2896 - 2.8224 44.1 11.2896 internal pll, master, normal speed 1 0 12.288 - 3.072 48 12.288 internal pll, master, double speed 1 1 - 22.5792 5.6448 88.2 22.5792 internal pll, master, double speed 1 1 - 24.576 6.144 96 24.576 internal pll, master, quad speed 1 0 - 22.5792 11.2896 176.4 22.5792 internal pll, master, quad speed 1 0 - 24.576 12.288 192 24.576 internal pll, slave, normal speed 0 0 - 8.192 2.0484 32 digital gnd internal pll, slave, normal speed 0 0 - 11.2896 2.8224 44.1 digital gnd internal pll, slave, normal speed 0 0 - 12.288 3.072 48 digital gnd internal pll, slave, double speed 0 1 - 22.5792 5.6448 88.2 digital gnd internal pll, slave, double speed 0 1 - 24.576 6.144 96 digital gnd internal pll, slave, quad speed || 0 0 - 22.5792 11.2896 176 digital gnd internal pll, slave, quad speed || 0 0 - 24.576 12.288 192 digital gnd ? a crystal oscillator is connected to xtl_in. ? mclk_in tied low when input to xtl_in is provided; xtl_in tied low when mclk_in_in is provided. external mclk_in connected to mclk_in_in input ? sclk and lrclk are outputs when m_s = 1, and inputs when m_s = 0. # mclk_out is driven low when m_s = 0. || quad-speed mode is detected automatically. sclk can be 48 or 64 times fs table 2?3. lrclk and mclk_in rates normal speed (khz) double speed (khz) quad speed (khz) lrclk 1 fs 32 44.1 48 1 fs 64 88.2 96 1 fs 176.4 192 mclk_in 256 fs 8,192 11,289.6 12,288 256 fs 16,384 22,579.2 24,576 128 fs 22,579.2 24,576 2.1.5 pll external filter a low jitter pll produces the internal timing of the TAS5026A (when in master mode), the master clock, sclk, and lrclk. connections for the pll external filter are provided through pll_flt_out and pll_fl t_ret as shown in figure 2?2. pll_flt_out TAS5026A pll_flt_ret 220 ? 47 nf 4.7 nf figure 2?2. pll external filter
architecture overview 11 sles068a?february 2003?revised january 2004 TAS5026A 2.1.6 dclk dclk is the internal high frequency clock that is produced by the pll circuitry from mclk. the TAS5026A uses the dclk to control all internal operations. dclk is 8 times the speed of mclk in normal speed mode, 4 times mclk in double speed, and 2 times mclk in quad speed. with respect to the i 2 c addressable registers, dclk clock cycles are used to specify interchannel delay and to detect when the mclk frequency is drifting. table 2?4 dclk shows the relationship between sample rate, mclk, and dclk. table 2?4. dclk fs (khz) mclk (mhz) dclk (mhz) dclk period (ns) 32 8.1920 65.5360 15.3 44.1 11.2896 90.3168 11.1 48 12.2880 98.3040 10.2 88 22.5280 90.1120 11.1 96 24.5760 98.3040 10.2 192 49.1520 98.3040 10.2 2.1.7 serial data interface the TAS5026A operates as a slave only/receive only serial data interface in all modes. the TAS5026A has three pcm serial data interfaces to accept six channels of digital data though the sdin1, sdin2, sdin3 inputs. the serial audio data is in msb first; 2s complement format. the serial data interfaces of the t as5026a can be configured in right justified, i 2 s, left-justified, or dsp modes. this interface supports 32-khz, 44.1-khz, 48-khz, 88-khz, 96-khz, 176.4-khz, and 192-khz data sample rates. the serial data interface format is specified using the data interface control register . the supported word lengths are shown in table 2?5. during normal operating conditions if the serial data interface settings change state, an error recovery sequence is initiated. table 2?5. supported word lengths data modes word lengths mod2 mod1 mod0 right justified, msb first 16 0 0 0 right justified, msb first 20 0 0 1 right justified, msb first 24 0 1 0 i 2 s 16 0 1 1 i 2 s 20 1 0 0 i 2 s 24 1 0 1 left justified, msb first 24 1 1 0 dsp frame 16 1 1 1
architecture overview 12 sles068a?february 2003?revised january 2004 TAS5026A 2.1.7.1 i 2 s timing i 2 s timing uses an lrclk to define when the data being transmitted is for the left channel and when it is for the right channel. the lrclk is low for the left channel and high for the right channel. a bit clock running at 48 or 64 times fs is used to clock in the data. there is a delay of one bit clock from the time the lrclk signal changes state to the first bit of data on the data lines. the data is written msb first and is valid on the rising edge of the bit clock. the TAS5026A masks unused trailing data bit positions. master mode only supports a 64 times fs bit clock. 23 22 sclk 32 clks lrclk (note reversed phase) left channel 24-bit mode 9 8 5 4 1 0 19 18 20-bit mode 5 4 1 0 16-bit mode 1 0 15 14 msb lsb 23 22 sclk 32 clks right channel 9 8 5 4 1 0 19 18 5 4 1 0 1 0 15 14 msb lsb 2-channel i 2 s (philips format) stereo input figure 2?3. i 2 s 64-fs format 2-channel i 2 s stereo input/output (24-bit transfer word size) 23 22 sclk 24 clks lrclk left channel 24-bit mode 20 19 8 7 2 1 19 18 20-bit mode 16 15 1 0 16-bit mode 1 0 15 14 msb lsb 4 3 5 21 4 5 17 13 12 11 23 22 sclk 24 clks right channel 20 19 8 7 2 1 19 18 16 15 1 0 1 0 15 14 msb lsb 4 3 5 21 4 5 17 13 12 11 0 figure 2?4. i 2 s 48-fs format
architecture overview 13 sles068a?february 2003?revised january 2004 TAS5026A 2.1.7.2 left-justified timing left-justified (lj) timing uses an lrclk to define when the data being transmitted is for the left channel and when it is for the right channel. the lrclk is high for the left channel and low for the right channel. a bit clock running at 48 or 64 times fs is used to clock in the data. the first bit of data appears on the data lines at the same time the lrclk toggles. the data is written msb first and is valid on the rising edge of the bit clock. the TAS5026A masks unused trailing data bit positions. master mode only supports a 64 times fs bit clock. 23 22 sclk 32 clks lrclk left channel 24-bit mode 9 8 5 4 1 0 msb lsb 2-channel left-justified stereo input 23 22 32 clks lrclk right channel 9 8 5 4 1 0 msb lsb note: all data presented in 2s complement form with msb first. figure 2?5. left-justified 64-fs format 22 21 sclk 24 clks lrclk left channel 19 9 8 1 0 msb lsb 2-channel left-justified stereo input/output (24-bit transfer word size) 3 2 4 20 23 22 21 24 clks right channel 19 9 8 1 0 msb lsb 3 2 4 20 23 5 5 24-bit mode figure 2?6. left-justified 48-fs format 2.1.7.3 right-justified timing right-justified (rj) timing uses an lrclk to define when the data being transmitted is for the left channel and when it is for the right channel. the lrclk is high for the left channel and low for the right channel. a bit clock running at 48 or 64 times fs is used to clock in the data. the first bit of data appears on the data 8-bit clock periods (for 24-bit data) after lrclk toggles. in rj mode, the last bit clock before lrclk transitions always clocks the lsb of data. the data is written msb first and is valid on the rising edge of the bit clock. the TAS5026A masks unused leading data bit positions. master mode only supports a 64 times fs bit clock.
architecture overview 14 sles068a?february 2003?revised january 2004 TAS5026A 23 22 sclk 32 clks lrclk left channel 24-bit mode 19 18 15 14 1 0 19 18 20-bit mode 15 14 1 0 16-bit mode 1 0 15 14 msb lsb 2-channel right-justified (sony format) stereo input note: all data presented in 2s complement form with msb first. 23 22 32 clks right channel 19 18 15 14 1 0 19 18 15 14 1 0 1 0 15 14 msb lsb figure 2?7. right-justified 64-fs format 22 21 sclk 24 clks lrclk left channel 19 1 0 19 1 0 msb lsb 2-channel right-justified stereo input/output (24-bit transfer word size) 20 23 note: all data presented in 2s complement form with msb first. 1 0 8 9 15 14 18 18 8 9 8 9 15 14 15 14 22 21 24 clks right channel 19 1 0 19 1 0 msb lsb 20 23 1 0 8 9 15 14 18 18 8 9 8 9 15 14 15 14 24-bit mode 20-bit mode 16-bit mode figure 2?8. right-justified 48-fs format
architecture overview 15 sles068a?february 2003?revised january 2004 TAS5026A 2.1.7.4 dsp mode timing dsp mode timing uses an lrclk to define when data is to be transmitted for both channels. a bit clock running at 64 fs is used to clock in the data . the first bit of the left channel data appears on the data lines following the lrclk transition. the data is written msb first and is valid on the rising edge of the bit clock. the TAS5026A masks unused trailing data bit positions. sclk lrclk 64 sclks lsb msb 16 bits left channel 16 bits right channel 32 bits unused sdin lsb msb figure 2?9. dsp format 2.2 reset, power down, and status the reset, power down, and status circuitry provides the necessary controls to bring the TAS5026A to the initial inactive condition, achieve low power standby, and report system status. 2.2.1 reset?reset the TAS5026A is placed in the reset mode by setting the reset terminal low. reset is an asynchronous control signal that restores the TAS5026A to its default conditions, sets the valid 1?6 outputs low, and places the pwm in the hard mute state. volume is immediately set to full attenuation (there is no ramp down). as long as the reset terminal is held low, the device is in the reset state. during reset, all i 2 c and serial data bus operations are ignored. table 2?6 shows the device output signals while reset is active. upon the release of reset , if power_dwn is high, the system performs a 4-ms to 5-ms device initialization and then ramps the volume up to 0 db using a soft volume update sequence. if mclk_in is not active when reset is released high, then a 4-ms to 5-ms initialization sequence is produced once mclk_in becomes active. during device initialization all controls are reset to their initial states. table 2?7 shows the control settings that are changed during initialization. reset should be applied during power-up initialization or while changing the master slave clock states.
architecture overview 16 sles068a?february 2003?revised january 2004 TAS5026A table 2?6. device outputs during reset signal mode signal state valid 1?valid 6 all low pwm p-outputs all low pwm m-outputs all low mclkout all low sclk master low sclk slave signal input lrclk master low lrclk slave signal input sda all signal input clip all high because the reset is an asynchronous control signal, small clicks and pops can be produced during the application (the leading edge) of this control. however, when reset is released, the transition from the hard mute state back to normal operation is performed synchronously using a quiet sequence. if a completely quiet reset sequence is desired, mute should be applied before applying reset . table 2?7. values set during reset control setting volume 0 db mclk_in frequency 256 master/slave mode m_s terminal state automute enabled de-emphasis none dc offset 0 interchannel delay each channel is set to a default value 2.2.2 power down?pdn the TAS5026A can be placed into the power-down mode by holding the pdn terminal low. when power-down mode is entered, both the pll and the oscillator are shut down. volume is immediately set to full attenuation (there is no ramp down). the valid 1?6 outputs are immediately asserted low and the pwm outputs are placed in the hard mute state. pdn initiates device power down without clock inputs. as long as the pdn terminal is held low?the device is in the power-down (hard mute) state. during power down, all i 2 c and serial data bus operations are ignored. table 2?8 shows the device output signals while pdn is active. table 2?8. device outputs during power down signal mode signal state valid 1?valid 6 all low pwm p-outputs all low pwm m-outputs all low mclkout all low sclk master low sclk slave signal input lrclk master low lrclk slave signal input sda all signal input clip all high to place the device in total power-down mode, both reset and power-down modes must be enabled. prior to bringing pdn high, reset must be brought low for a minimum of 50 ns.
architecture overview 17 sles068a?february 2003?revised january 2004 TAS5026A because pdn is an asynchronous control signal, small clicks and pops can be produced during the application (the leading edge) of this control. however, when pdn is released, the transition from the hard mute state back to normal operation is performed synchronously using a quiet sequence. if a completely quiet reset sequence is desired, mute should be applied before applying pdn . 2.2.2.1 recovery time options to support the requirements of various system configurations, the t as5026a can come up to the normal state after either a long (100 ms) or a short (5 ms) delay. 1. in the first case, a slow system (95 ms to 100 ms) start-up occurs at the end of the power-down sequence when: reset is high for at least 16 mclk_in periods before pdn goes high. 2. otherwise a fast (4 ms to 5 ms) start-up occurs. note: if mclk_in is not active when both of these signals are released high, then a fast (4 ms to 5 ms) start-up occurs once mclk_in becomes active. 2.2.3 general status registers the general status register is a read only register. this register provides an indication when a volume update is in progress or one of the channels is inactive. the device id can be read using this register. volume update is in progress? whenever a volume change is in progress due to a volume update command or mute, this status bit is high. device identification code? the device identification code, 1 0011, is displayed. no internal errors (all valid signals are high)? when there are no internal errors in the TAS5026A and all outputs are valid, this status bit is high. one or more valid signals are inactive? if low, one or more channels of the TAS5026A are not outputting data. the valid signals for those channels are inactive. this can be produced by one of three causes: ? one or more of the clock signals are in error ? error recover is active (low) ? the automute has silenced one or more channels that are receiving 0 inputs ? mute has been set ? volume control has been set to full attenuation if this signal is high, the TAS5026A is outputting data on all channels. 2.2.4 error status register the error status register indicates historical information on control signal changes and clock errors. this register latches these indications when they occur. the indications are cleared by writing a 00(hex) to the register. this register is intended as a diagnostic tool to be used only when the system is not operating correctly. this is because the error status bits are set when the data rate, serial data interface format, or master/slave mode is changed. as a result, this register indicates an error condition ev en though the syst em is operating normally. this register should only be used while diagnosing transient error conditions. any clock error or control signal terminal change which occurs since the last time the error status register was cleared is displayed. in using this register, the first step is to initialize the device and ve rify that all of the clock signals are active. then this register should be cleared by writing a 00(hex). at this point, the register indicates any errors or control signal changes.
architecture overview 18 sles068a?february 2003?revised january 2004 TAS5026A this register indicates an error condition by a high for the following conditions: ? fs error ? a control terminal change has occurred (m_s , dblspd) ? lrclk error ? mclk_in count error ? dclk phase error with respect to mclk_in ? mclk_in phase error with respect to dclk ? pwm timing error if all bits of the register are low, no errors have occurred and no control terminals changed. there is no one-to-one correspondence of clock error indication to a system error condition. a particular system error can be indicated by one or more error indications in this register. the system error conditions and the reported errors are as follows: there is no correct number of mclks per lrclk: ? fs error has occurred ? lrclk error ? mclk_in count error lrclk is absent: ? lrclk error mclk is the wrong frequency, changing frequency, or absent: ? dclk phase error with respect to mclk ? mclk phase error with respect to dclk ? pwm timing error sclk is the wrong frequency or absent: ? sclk error 2.3 signal processing this section contains the signal processing functions that are contained in the TAS5026A. the signal processing is performed using a high-speed 24-bit signal processing architecture. the TAS5026A performs the following signal processing features: ? individual channel soft volume with a range of 24 db to ?114 db plus mute ? soft mute ? automute ? 50- s/15- s de-emphasis filter supported in the sampling rates 32 khz, 44.1 khz, and 48 khz 2.3.1 volume control the gain of each output can be adjusted by a soft digital volume control for each channel. v olume adjustments are performed using a soft gain update s-curve, which is approximated using a second order filter fit. the curve fit is performed over a transition interval between 41 ms and 65 ms. the volume of each channel can be adjusted from mute to ?114 db to 24 db in 0.5 db steps. because of the numerical representation that is used to control the volume, at very low volume levels the step size increases for gains that are less than ?96 db. the default volume setting following power up or reset is 0 db for all channels. the step size adjustment is linear down to approximately ?90 db, see see figure 2?10.
architecture overview 19 sles068a?february 2003?revised january 2004 TAS5026A attenuation (gain) ? db 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 step size ? db step size vs attenuation (gain) figure 2?10. attenuation curve the volume control format for each channel is expressed in 8 bits. the volume for each channel is set by writing 8 bits via the serial control interface. the msb bit is written first as in the bit position 0 (lsb position). the volume for each channel can be set using a single or multiple address write operation to the volume control register via the serial control interface. changing the volume of all six channels requires that 6 registers be updated. to coordinate the volume adjustment of multiple channels simultaneously, the t as5026a performs a delayed volume update upon receiving a volume change command. following the completion of the register volume write operations, the TAS5026A waits for 5 ms for another volume command to be given. if no volume command is issued in that period of time, the TAS5026A starts adjusting the volume of the channels that received volume settings. while a volume update is being performed, the system status register indicates that the update is in progress. during the update, all subsequent volume c ontrol setting requests that are sent to the TAS5026A are received and stored as a single next value for a subsequent update. if more than one volume setting request is sent, only the last is retained. table 2?9. volume register volume register d7 d6 d5 d4 d3 d2 d1 d0 vol bit 7 vol bit 6 vol bit 5 vol bit 4 vol bit 3 vol bit 2 vol bit 1 vol bit 0 2.3.2 mute the application of mute ramps the volume from any setting to noiseless hard mute state. there are two methods in which the TAS5026A can be placed into m ute. the TAS5026A is placed in the noiseless mute when the mute terminal is asserted low for a minimum of 3 mclk_in cycles. alternatively, the mute mode can be initiated by setting the mute bit in the system control register through the serial control interface. the TAS5026A is held in mute state as long as the terminal is low or i 2 c mute setting is active. this command uses quiet entry and exit sequences to and from the hard mute state.
architecture overview 20 sles068a?february 2003?revised january 2004 TAS5026A if an error recovery (described in the pwm section) occurs after a mute request has been received, the device returns from error recovery with the channel volume set as specified by the mute command. 2.3.3 automute automute is an automatic sequence that can be enabled or disabled via the serial control interface. the default for this control is enabled. when enabled, the pwm automutes an individual channel when a channel receives from 5 ms to 50 ms of consecutive zeros. this time interval can be selectable using the automute delay register. the default interval is 5 ms at 48 khz. this duration is independent of the sample rate. the automute state is exited when two consecutive samples of nonzero data are received. the TAS5026A exit from automute is performed quickly and preserves all music information. this mode uses the valid low to provide a low-noise floor while maintaining a short start-up time. noise free entry and exit is achieved by using the pwm quiet start and stop sequences. 2.3.4 individual channel mute individual channel mute is invoked through the serial interface. individual channel mute permits each channel of the t as5026a to be individually muted and unmuted. the operation that is performed is identical to the mute operation; however, it is performed on a per channel basis. a TAS5026A channel is held in the mute state as long as the serial interface mute setting for that channel is set. 2.3.5 de-emphasis filter for audio sources that have been pre-emphasized, a precision 50- s/15- s de-emphasis filter is provided to support the sampling rates of 32 khz, 44.1 khz, and 48 khz. see figure 2?11 for a graph showing the de-emphasis filtering characteristics. de-emphasis is set using two bits in the system control register. table 2?10. de-emphasis filter characteristics dem_sel2 (msb) dem_sel1 description 0 0 de-emphasis disabled 0 1 de-emphasis enabled for fs = 48 khz 1 0 de-emphasis enabled for fs = 44 khz 1 1 de-emphasis enabled for fs = 32 khz following the change of state of the de-emphasis bits, the pwm outputs go into the soft mute state. after 128 lrclk periods for initialization, the pwm outputs are driven to the normal (unmuted) mode. 0 ?10 response ? db 3.18 (50 s) 10.6 (15 s) f ? frequency ? khz de-emphasis figure 2?11. de-emphasis filter characteristics 2.4 pulse-width modulator (pwm) the TAS5026A contains six channels of high performance digital equibit pwm modulators that are designed to drive switching output stages (back ends) in both single-ended (se) and h-bridge (bridge tied load) configuration. the TAS5026A device uses noise shaping and sophisticated error correction algorithms to achieve high power efficiency and high-performance digital audio reproduction. the pwm provides six pseudo-differential outputs to drive six monolithic power stages (such as tas5110) or six discrete differential power stages using of gate drivers (such as the tas5182) and mosfets in single-ended or bridged configurations. the TAS5026A also provides a high performance differential output that can be used to drive an external analog headphone amplifier.
architecture overview 21 sles068a?february 2003?revised january 2004 TAS5026A 2.4.1 clipping indicator the clipping output is designed to indicate clipping. when any of the six pwm outputs exceeds the maximum allowable amplitude, the clipping indicator is asserted. the clipping indicator is cleared every 10 ms. 2.4.2 error recovery error recovery is used to provide error management and to permit the pwm output to be reset while preserving all intervolume, interchannel delay, dc offsets, and the other internal settings. error recovery is initiated by bringing the err_rcvry terminal low for a minimum 5 mclk_in cycles or by setting the error recovery bit in control register 1. error recovery is a level sensitive signal. the device also performs an error recovery automatically: ? when the speed configuration is changed to normal, double, or quad speed ? following a change in the serial data bus interface configuration when err_rcvry is brought low, all valid signals go low, and the pwm-p and pwm-m outputs go low. if there are any pending speed configurations, these changes are then performed. when err_rcvry is brought high, a delay of 4 ms to 5 ms is performed before the system starts the output re-initialization sequence. after the initialization time, the TAS5026A begins normal operation. during error recovery, all controls and device settings that were not updated are maintained in their current configurations. to permit error recovery to be used to provide t as5100 error management and recovery, the delay between the start of (falling edge) error recovery and the falling edge of valid 1 though valid 6 is selectable. this delay can be selected to be either 6 s or 47 s. during error recovery all serial data bus operations are ignored. at the conclusion of the sequence, the error recovery register bit is returned to normal operation state. table 2?11 shows the device output signal states while during error recovery. table 2?11. device outputs during error recovery signal mode signal state valid 1?valid 6 all low pwm p-outputs all low pwm m-outputs all low mclkout all low sclk master low sclk slave signal input lrclk master low lrclk slave signal input sda all signal input clip all high the transitions are done using a quiet entrance and exit sequence to prevent pops and clicks. 2.4.3 individual channel error recovery individual channel error recovery is used to provide error management and to permit the pwm output to be turned off. error recovery is initiated by setting one or more of the six error recovery bits in the error recovery register to low. while the error recover bits are brought low, the valid signals go to the low state. when the error recovery bits are brought high, a delay of 4 ms to 5 ms occurs before the channels are returned to normal operation. the delay between the falling edge of the error recover bit and the falling edge of valid 1 though valid 6 is selectable. this delay can be selected to be either 6 s or 47 s. the TAS5026A controls the relative timing of the pseudo-differential drive control signals plus the valid signal to minimize the production of system noise during error recovery operations. the transitions to valid low and valid high are done using an almost quiet entrance and exit sequence to prevent pops and clicks.
architecture overview 22 sles068a?february 2003?revised january 2004 TAS5026A 2.4.4 pwm dc-offset correction an 8-bit value can be programmed to each of the six pwm offset correction registers to correct for any offset present in the output stages. the offset correction is divided into 256 intervals with a total offset correction of 1.56% of full scale. the default value is zero correction represented by 00 (hex). these values can be changed at any time through the serial control interface. 2.4.5 interchannel delay an 8-bit value can be programmed to each of the six pwm interchannel delay registers to add a delay per channel from 0 to 255 clock cycles. the delays correspond to cycles of the high-speed internal clock, dclk. each subsequent channel has a default value that is n dclks larger than the preceding channel. the default values are 0 for the first channel and 76 for each successive channel. these values can be updated upon power up through the serial control interface. this delay is generated in the pwm block with the appropriate control signals generated in the ctl block. these values can be changed at any time through the serial control interface. note: the performance of a purepath digital ? amplifier system is optimized by setting the pwm timing based upon the type of back-end device that is used and the layout. these values are set during initialization using the i 2 c serial interface. 2.4.6 pwm/h-bridge and discrete h-bridge driver interface the TAS5026A provides six pwm outputs, which are designed to drive switching output stages (back-ends) in both single-ended (se) and h-bridge (bridge tied load) configuration. the back-ends may be monolithic power stages (such as the t as5110) or six discrete differential power stages using gate drivers (such as the the tas55182) and mosfets in single-ended or bridged configurations. the tas5110 device is optimized for bridge tied load (btl) configurations. these devices require a pure differential pwm signal with a third signal (valid) to control the mute state. in the mute state, the t as5110 outa and outb are both low. one channel of TAS5026A pwm_ap pwm_am valid tas5110 outa outb ap am reset bp bm speaker figure 2?12. pwm outputs and h-bridge driven in btl configuration 2.5 i 2 c serial control interface mclk must be active for the TAS5026A to support i 2 c bus transactions. the TAS5026A has a bidirectional serial control interface that is compatible with the i 2 c (inter ic) bus protocol and supports both 100 kbps and 400 kbps data transfer rates for single and multiple byte write and read operations. this is a slave only device that does not support a multi-master bus environment or wait state insertion. the control interface is used to program the registers of the device and to read device status. the TAS5026A supports the standard-mode i 2 c bus operation (100 khz maximum) and the fast i 2 c bus operation (400 khz maximum). the TAS5026A performs all i 2 c operations without i 2 c wait cycles. purepath digital is a trademark of texas instruments.
architecture overview 23 sles068a?february 2003?revised january 2004 TAS5026A the i 2 c bus employs two signals; sda (data) and scl (clock), to communicate between integrated circuits in a system. data is transferred on the bus serially one bit at a time. the address and data are transferred in byte (8 bit) format with the most significant bit (msb) transferred first. in addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. the bus uses transitions on the data terminal (sda) while the clock is high to indicate start and stop conditions. a high-to-low transition on sda indicates a start, and a low-to-high transition indicates a stop. normal data bit transitions must occur within the low time of the clock period. these conditions are shown in figure 2?13. the master generates the 7-bit slave address and the read/write (r/w) bit to open communication with another device and then waits for an acknowledge condition. the TAS5026A holds sda low during acknowledge clock period to indicate an acknowledgement. when this occurs, the master transmits the next byte of the sequence. each device is addressed by a unique 7-bit slave address plus r/w bit (1 byte). all compatible devices share the same signals via a bidirectional bus using a wired-and connection. i 2 c an external pullup resistor must be used for the sda and scl signals to set the high level for the bus. 7 bit slave address r/ w 8 bit register address (n) a 8 bit register data for address (n) start sto p sda scl 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 a 7 6 5 4 3 2 1 0 8 bit register data for address (n) 7 6 5 4 3 2 1 0 aa figure 2?13. typical i 2 c sequence there are no limits on the number of bytes that can be transmitted between start and stop conditions. when the last word transfers, the master generates a stop condition to release the bus. a generic data transfer sequence is also shown in figure 2?13. the 7-bit address for the TAS5026A is 001101x, where x is a programmable address bit. using the cs0 terminal on the device, the lsb address bit is programmable to permit two devices to be used in a system. these two addresses are licensed i 2 c addresses and do not conflict with other licensed i 2 c audio devices. to communicate with the TAS5026A, the i 2 c master uses 0011010 if cs0 = 0 and 0011011 if cs0 = 1. in addition to the 7-bit device address, an 8-bit register address is used to direct communication to the proper register location within the device interface. read and write operations to the TAS5026A can be done using single byte or multiple byte data transfers. 2.5.1 single-byte write as shown in figure 2?14, a single byte data write transfer begins with the master device transmitting a start condition followed by the i 2 c device address and the read/write bit. the read/write bit determines the direction of the data transfer. for a write data transfer, the read/write bit is 0. after receiving the correct i 2 c device address and the read/write bit, the TAS5026A device responds with an acknowledge bit. next, the master transmits the address byte or bytes corresponding to the TAS5026A internal memory address being accessed. after receiving the address byte, the TAS5026A again responds with an acknowledge bit. next, the master device transmits the data byte to be written to the memory address being accessed. after receiving the data byte, the TAS5026A again responds with an acknowledge bit. finally, the master device transmits a stop condition to complete the single byte data write transfer.
architecture overview 24 sles068a?february 2003?revised january 2004 TAS5026A a6 a5 a4 a3 a2 a1 a0 r/w ack a7 a6 a5 a4 a3 a2 a1 a0 ack d7 d6 d5 d4 d3 d2 d1 d0 ack stop condition acknowledge acknowledge acknowledge i 2 c device address and read/write bit register address data byte start condition figure 2?14. single-byte write transfer 2.5.2 multiple-byte write a multiple byte data write transfer is identical to a single byte data write transfer except that multiple data bytes are transmitted by the master device to TAS5026A as shown in figure 2?15. after receiving each data byte, the TAS5026A responds with an acknowledge bit. d7 d6 d1 d0 ack stop condition acknowledge i 2 c device address and read/write bit register address last data byte a6 a5 a1 a0 r/w ack a7 a5 a1 a0 ack d7 d6 d1 d0 ack start condition acknowledge acknowledge acknowledge first data byte a4 a3 a6 other data bytes figure 2?15. multiple-byte write transfer 2.5.3 single-byte read as shown in figure 2?16, a single byte data read transfer begins with the master device transmitting a start condition followed by the i 2 c device address and the read/write bit. for the data read transfer, a write followed by a read are actually done. initially, a write is done to transfer the address byte or bytes of the internal memory address to be read. as a result, the read/write bit is 0. after receiving the t as5026a address and the read/write bit, the TAS5026A responds with an acknowledge bit. also, after sending the internal memory address byte or bytes, the master device transmits another start condition followed by the TAS5026A address and the read/write bit again. this time the read/write bit is a 1 indicating a read transfer. after receiving the t as5026a and the read/write bit, the TAS5026A again responds with an acknowledge bit. next, the t as5026a transmits the data byte from the memory address being read. after receiving the data byte, the master device transmits a not acknowledge followed by a stop condition to complete the single byte data read transfer. a6 a5 a0 r/w ack a7 a6 a5 a4 a0 ack a6 a5 a0 ack start condition stop condition acknowledge acknowledge acknowledge i 2 c device address and read/write bit register address data byte d7 d6 d1 d0 ack i 2 c device address and read/write bit repeat start condition not acknowledge r/w a1 a1 figure 2?16. single-byte read 2.5.4 multiple-byte read a multiple byte data read transfer is identical to a single byte data read transfer except that multiple data bytes are transmitted by the TAS5026A to the master device as shown in figure 2?17. except for the last data byte, the master device responds with an acknowledge bit after receiving each data byte. a6 a0 ack acknowledge i 2 c device address and read/write bit r/w a6 a0 r/w ack a4 a0 ack d7 d0 ack start condition stop condition acknowledge acknowledge acknowledge last data byte d7 d6 d1 d0 ack first data byte repeat start condition not acknowledge i 2 c device address and read/write bit register address other data bytes a7 a6 a5 figure 2?17. multiple-byte read
serial control interface register definitions 25 sles068a?february 2003?revised january 2004 TAS5026A 3 serial control interface register definitions table 3?1 shows the register map for the TAS5026A. default values in this section are in bold. table 3?1. i 2 c register map addr hex description 00 general status register 01 error status register 02 system control register 0 03 system control register 1 04 error recovery register 05 automute delay 06 dc-offset control register channel 1 07 dc-offset control register channel 2 08 dc-offset control register channel 3 09 dc-offset control register channel 4 0a dc-offset control register channel 5 0b dc-offset control register channel 6 0c interchannel delay register channel 1 0d interchannel delay register channel 2 0e interchannel delay register channel 3 0f interchannel delay register channel 4 10 interchannel delay register channel 5 11 interchannel delay register channel 6 12 reserved 13 volume control register channel 1 14 volume control register channel 2 15 volume control register channel 3 16 volume control register channel 4 17 volume control register channel 5 18 volume control register channel 6 19 individual channel mute the volume table is contained in appendix a. default values are shown in bold in the following tables.
serial control interface register definitions 26 sles068a?february 2003?revised january 2004 TAS5026A 3.1 general status register (0x00) table 3?2. general status register (read only) d7 d6 d5 d4 d3 d2 d1 d0 function 0 - - - - - - - no volume update is in progress. 1 - - - - - - - volume update is in progress. - 0 - - - - - - always 0 - - 1 0 0 1 1 - device identification code - - - - - - - 0 any valid signal is inactive (see status register (0x03)) (see note 1). - - - - - - - 1 no internal errors (all valid signals are high) note 1: this bit is reset automatically when one or more channels are active. 3.2 error status register (0x01) table 3?3. error status register d7 d6 d5 d4 d3 d2 d1 d0 function 1 - - - - - - - fs error has occurred - 1 - - - - - - control pin change has occurred - - - 1 - - - - lrclk error - - - - 1 - - - mclk_in count error - - - - - 1 - - dclk phase error with respect to mclk_in - - - - - - 1 - mclk_in phase error with respect to dclk - - - - - - - 1 pwm timing error 0 0 0 0 0 0 0 0 no errors?no control pins changed note 2: write 00 hex to clear error indications in error status register. 3.3 system control register 0 (0x02) table 3?4. system control register 0 d7 d6 d5 d4 d3 d2 d1 d0 function 0 0 - - - - - - normal mode (in slave mode?quad speed detected if mclk_in = 128 fs) 0 1 - - - - - - double speed 1 0 - - - - - - quad speed 1 1 - - - - - - illegal - - 0 - - - - - use de-emphasis pin controls - - 1 - - - - - use de-emphasis i2c controls - - - 0 0 - - - no de-emphasis - - - 0 1 - - - de-emphasis for fs = 32 khz - - - 1 0 - - - de-emphasis for fs = 44.1 khz - - - 1 1 - - - de-emphasis for fs = 48 khz - - - - - 0 0 0 16 bit, msb first; right justified - - - - - 0 0 1 20 bit, msb first; right justified - - - - - 0 1 0 24 bit, msb first; right justified - - - - - 0 1 1 16-bit i 2 s - - - - - 1 0 0 20-bit i 2 s - - - - - 1 0 1 24-bit i 2 s - - - - - 1 1 0 16-bit msb first - - - - - 1 1 1 16-bit dsp frame
serial control interface register definitions 27 sles068a?february 2003?revised january 2004 TAS5026A 3.4 system control register 1 (0x03) table 3?5. system control register 1 d7 d6 d5 d4 d3 d2 d1 d0 function 0 - - - - - - - reserved - 0 - - - - - - valid remains high during automute. - 1 - - - - - - valid goes low during automute. - - 0 - - - - - valid remains high during mute. - - 1 - - - - - valid goes low during mute. - - - 0 - - - - mute - - - 1 - - - - normal mode - - - - 0 - - - set error recovery delay at 6 s - - - - 1 - - - set error recovery delay at 47 s - - - - - 0 - - error recovery (forces error recovery initialization sequence) - - - - - 1 - - normal mode - - - - - - 0 - automute disabled - - - - - - 1 - automute enabled - - - - - - - 1 reserved 3.5 error recovery register (0x04) table 3?6. error recovery register d7 d6 d5 d4 d3 d2 d1 d0 function 1 1 ? ? ? ? ? ? set to 11 under default conditions and when x00 is written into 0x1f 0 ? ? ? ? ? ? ? if 0x84 is written into 0x1f ? enable volume ramp up after an error recovery sequence initiated by the err_rcvry terminal or the i 2 c error recovery command (register 0x03 bit d2). 1 ? ? ? ? ? ? ? if 0x84 is written into 0x1f ? disable volume ramp up after an error recovery sequence initiated by the err_rcvry terminal or the i 2 c error recovery command (register 0x03 bit d2) ? 0 ? ? ? ? ? ? if 0x84 is written into 0x1f ? enable volume ramp up after error recovery sequence initiated by register bits d5?d0 of this register. ? 1 ? ? ? ? ? ? if 0x84 is written into 0x1f ? enable volume ramp up after error recovery sequence initiated by register bits d5?d0 of this register. ? ? 0 ? ? ? ? ? put channel 6 into error recovery mode ? ? ? 0 ? ? ? ? put channel 5 into error recovery mode ? ? ? ? 0 ? ? ? put channel 4 into error recovery mode ? ? ? ? ? 0 ? ? put channel 3 into error recovery mode ? ? ? ? ? ? 0 ? put channel 2 into error recovery mode ? ? ? ? ? ? ? 0 put channel 1 into error recovery mode ? ? 1 1 1 1 1 1 normal operation
serial control interface register definitions 28 sles068a?february 2003?revised january 2004 TAS5026A 3.6 automute delay register (0x05) table 3?7. automute delay register d7 d6 d5 d4 d3 d2 d1 d0 function 0 0 0 0 - - - - reserved - - - - 0 0 0 0 set automute delay at 5 ms - - - - 0 0 0 1 set automute delay at 10 ms - - - - 0 0 1 0 set automute delay at 15 ms - - - - 0 0 1 1 set automute delay at 20 ms - - - - 0 1 0 0 set automute delay at 25 ms - - - - 0 1 0 1 set automute delay at 30 ms - - - - 0 1 1 0 set automute delay at 35 ms - - - - 0 1 1 1 set automute delay at 40 ms - - - - 1 - - 0 set automute delay at 45 ms - - - - 1 - - 1 set automute delay at 50 ms 3.7 dc-offset control registers (0x06?0x0b) channels 1, 2, 3, 4, 5, and 6 are mapped into (0x06, 0x07, 0x08, 0x09, 0x0a, and 0x0b). table 3?8. dc-offset control registers d7 d6 d5 d4 d3 d2 d1 d0 function 1 0 0 0 0 0 0 0 maximum correction for positive dc offset (?1.56% fs) 0 0 0 0 0 0 0 0 no dc-offset correction 0 1 1 1 1 1 1 1 maximum correction for negative dc offset (1.56% fs) 3.8 interchannel delay registers (0x0c?0x11) channels 1, 2, 3, 4, 5, and 6 are mapped into (0x0c, 0x0d, 0x0e, 0x0f, 0x10, and 0x11). the first channel delay is set at 0. each subsequent channel has a default value that is 76 dclks larger than the preceding channel. table 3?9. six interchannel delay registers d7 d6 d5 d4 d3 d2 d1 d0 function 0 0 0 0 0 0 0 0 minimum absolute delay, 0 dclk cycles, default for channel 1 0 1 0 0 1 1 0 0 default for channel 2 1 0 0 1 1 0 0 0 default for channel 3 1 1 1 0 0 1 0 0 default for channel 4 0 0 1 1 0 0 0 0 default for channel 5 0 1 1 1 1 1 0 0 default for channel 6 1 1 1 1 1 1 1 1 maximum absolute delay, 255 dclk cycles
serial control interface register definitions 29 sles068a?february 2003?revised january 2004 TAS5026A 3.9 individual channel mute register (0x19) table 3?10. individual channel mute register d7 d6 d5 d4 d3 d2 d1 d0 function 1 1 - - - - - - reserved - - 1 1 1 1 1 1 no channels are muted - - - - - - - 0 mute channel 1 - - - - - - 0 - mute channel 2 - - - - - 0 - - mute channel 3 - - - - 0 - - - mute channel 4 - - - 0 - - - - mute channel 5 - - 0 - - - - - mute channel 6
serial control interface register definitions 30 sles068a?february 2003?revised january 2004 TAS5026A
system procedures for initialization, changing data rates, and switching between master and slave modes 31 sles068a?february 2003?revised january 2004 TAS5026A 4 system procedures for initialization, changing data rates, and switching between master and slave modes 4.1 system initialization reset is used during system initialization to hold the t as5026a inactive while power (vdd), the master clock (mclk_in), the device control, and the data signals become stable. the recommended initialization sequence is to hold reset low for 24 mclk_in cycles after vdd has reached 3 v and the other control signals (mute , pdn , m_s, err_rcvry , dbspd, and cs0) are stable. figure 4?1 shows the recommended sequence and timing for the reset terminal relative to system vdd voltage and mclk. mclk vdd 3 v 24 mclk_in cycles reset figure 4?1. reset during system initialization within the first 2 ms following the low to high transition of the reset terminal, the serial data interface format should be set in the serial data interface control register using the i 2 c serial control interface. if the data rate setting is other than the setting specified by the dbspd terminal, then the data rate should be set using the dbspd terminal or i 2 c interface within 2 ms, following the low to high transition of the reset terminal. the time available to set the i 2 c registers following the low to high transition of the reset terminal can be extended using the err_rcvry terminal. while err_rcvry is low, the TAS5026A outputs are held inactive. once the i 2 c control registers are set, the err_rcvry terminal can be released and the t as5026a starts operation. figure 4?2 shows how err_rcvry terminal can be used to extend the interval as long as necessary to set the i 2 c registers following the low-to-high transition of the reset terminal.
system procedures for initialization, changing data rates, and switching between master and slave modes 32 sles068a?february 2003?revised january 2004 TAS5026A < 2 ms mclk reset e rr_rcvry err_rcvry and mute can be set at any time prior to 2 ms following the low-to-high transition of reset mute wait a minimum of 100 s after the low-to-high transition of reset > 5 ms release err_rcvry and then mute when i 2 c registers are programmed volume ramp up 120 ms set serial interface format, data rate, volume, ... via i 2 c figure 4?2. extending the i 2 c write interval following low-to-high transition of reset terminal the operation of the TAS5026A can be tailored as desired to meet specific operating requirements by adjusting the following: ? volume ? data sample rate ? emphasis/deemphasis settings ? individual channel mute ? automute delay register ? dc-offset control registers if desired, the TAS5026A can be set to perform an unmute sequence following the low-to-high transition of the err_rcvry terminal or the error recovery i 2 c command (register x03 bit d2). this capability is set by writing x7f to the individual error recovery register (x04) and an x84 to x1f (a feature enable register). 4.2 data sample rate if the master clock is well-behaved during the frequency transition (no mclk_in high or low clock periods less than 20 ns), then a simple speed selection is performed by setting the dbspd terminal or the serial control register. if it is known at least 60 ms in advance that the sample rate changes, mute can be used to provide a completely silent transition. the timing of this control sequence is shown in figure 4?3 and figure 4?4.
system procedures for initialization, changing data rates, and switching between master and slave modes 33 sles068a?february 2003?revised january 2004 TAS5026A mclk mute terminal dbspd terminal change from a 96-khz data rate mclk_in = 24.576 mhz clock transition change to a 48-khz data rate mclk_in = 12.288 mhz volume ramp up 42 ? 65 ms > 5 ms < 2 ms < 2 ms volume ramp down 42 ? 65 ms set within 2 ms of transition figure 4?3. changing the data sample rate using the dbspd terminal mclk mute terminal change from a 96-khz data rate mclk_in = 24.576 mhz clock transition change to a 48-khz data rate mclk_in = 12.288 mhz volume ramp up 42 ? 65 ms > 5 ms < 2 ms < 2 ms volume ramp down 42 ? 65 ms e rr_rcvry terminal hold err_rcvry low to give additional timeset registers set data rate via i 2 c register 0x02, d7 and d6 figure 4?4. changing the data sample rate using the i 2 c however, if the master clock input can encounter a high clock or low clock period of less than 20 ns, then reset should be applied during this time. there are two recommended control procedures for this case, depending upon whether the dbspd terminal or the serial control interface is used. these control sequences are shown in figure 4?5 and figure 4?6. because this sequence employs the reset terminal, the internal register settings are set to the default values.
system procedures for initialization, changing data rates, and switching between master and slave modes 34 sles068a?february 2003?revised january 2004 TAS5026A figure 4?5 shows the procedure to change the data rate using the dbspd terminal and then to restore the register settings. in this example, the err_rcvry terminal is used to hold off system re-initialization after reset is released. this permits the system controller to have as much additional time as necessary to restore the register settings. once the data rate is set, the err_rcvry and mute terminal signals are set high and the system re-initializes. mclk mute terminal e rr_rcvry terminal change from a 96-khz data rate mclk_in = 24.576 mhz clock unstable during transition. high and low intervals < 20 ns change to a 48-khz data rate mclk_in = 12.288 mhz volume ramp up 120 ms volume ramp down 60 ms err_rcvry can be set at any time within this interval wait a minimum of 100 s after the low to high transition of reset release err_rcvry and then mute when i 2 c registers are programmed > 5 ms reset terminal dbspd terminal < 2 ms wait a minimum of 100 s to set dbspd restore register settings via i 2 c figure 4?5. changing the data sample rate with an unstable mclk_in using the dbspd terminal because this sequence employs the reset terminal, the internal register settings are set to the default values. figure 4?5 shows the procedure to change the data rate using register 0x02 bits d7 and d6 and then to restore the other register settings. in this example, the err_rcvry terminal is used to hold off system re-initialization after reset is released. this permits the system controller to have as much additional time as necessary to restore the register settings. once the data rate is set, the err_rcvry and mute terminal signals are set high and the system re-initializes.
system procedures for initialization, changing data rates, and switching between master and slave modes 35 sles068a?february 2003?revised january 2004 TAS5026A mclk mute terminal e rr_rcvry terminal change from a 96-khz data rate mclk_in = 24.576 mhz clock unstable during transition. high and low intervals < 20 ns change to a 48-khz data rate mclk_in = 12.288 mhz volume ramp up 120 ms volume ramp down 60 ms err_rcvry can be set at any time within this interval wait a minimum of 100 s after the low to high transition of reset release err_rcvry and then mute when i 2 c registers are programmed > 5 ms reset terminal < 2 ms set data rate and restore other register settings via i 2 c figure 4?6. changing the data sample rate with an unstable mclk_in using the i 2 c 4.3 changing between master and slave modes the master and slave mode is set while the reset terminal is active. because this sequence employs the reset terminal the internal register settings are set to the default values. figure 4?7 shows the procedure to switch between master and slave modes and then restore the register settings. in this example, the err_rcvry terminal is used to hold off system re-initialization after reset is released. this permits the system controller to have as much additional time as necessary to restore the register settings. once the data rate is set, the err_rcvry and mute terminal signals are set high and the system re-initializes.
system procedures for initialization, changing data rates, and switching between master and slave modes 36 sles068a?february 2003?revised january 2004 TAS5026A mclk mute terminal e rr_rcvry terminal change from master mode clock unstable during transition. change to slave mode volume ramp up 120 ms volume ramp down 60 ms err_rcvry can be set at any time within this interval wait a minimum of 100 s after the low to high transition of reset release err_rcvry and then mute when i 2 c registers are programmed > 5 ms reset terminal m_s terminal < 2 ms wait a minimum of 100 s to set m_s restore register settings via i 2 c figure 4?7. changing between master and slave clock modes
specifications 37 sles068a?february 2003?revised january 2004 TAS5026A 5 specifications 5.1 absolute maximum ratings over operating temperature ranges (unless otherwise noted) ? digital supply voltage range: dvdd_core, dvdd_pwm, dvdd_rcl ?0.3 v to 4.2 v . . . . . . . . . . . . . . . . . . analog supply voltage range: avdd_pll, add_osc ?0.3 v to 4.2 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . digital input voltage range, v i ?0.3 v to dvddx + 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating free-air temperature, TAS5026A 0 c to 70 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg ?65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . esd 2000 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, a nd functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating conditi ons? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 5.2 recommended operating conditions min typ max unit supply voltage digital dv ddx , see note 1 3 3.3 3.6 v supply current digital operating 60 ma supply current digital power down, see note 2 25 a power dissipation digital operating 200 mw power dissipation digital power down 100 w supply voltage analog av ddx , see note 3 3 3.3 3.6 v supply current analog operating 10 ma supply current analog power down, see note 2 25 a power dissipation analog operating 35 mw power dissipation analog power down, see note 2 100 w notes: 3. dvdd_core, dvdd_pwm, dvdd_rcl 4. if the clocks are turned off. 5. avdd_pll, avdd_osc 5.3 electrical characteristics over recommended operating conditions 5.3.1 static digital specifications over recommended operating conditions (unless otherwise noted) parameter test conditions min max unit v ih high-level input voltage 2 dvdd1 v v il low-level input voltage 0 0.8 v v oh high-level output voltage i o = ?1 ma 2.4 v v ol low-level output voltage i o = 4 ma 0.4 v i lkg input leakage current ?10 10 a 5.3.2 digital interpolation filter and pwm modulator over recommended operating conditions (unless otherwise noted) (fs = 48 khz) parameter test conditions min typ max unit pass band 0 20 khz pass band ripple 0.012 db stop band 24.1 khz stop band attenuation 24.1 khz to 152.3 khz 50 db group delay 700 s pwm modulation index (gain) 0.93%
specifications 38 sles068a?february 2003?revised january 2004 TAS5026A 5.3.3 TAS5026A/tas5110 system performance measured at the speaker terminals over recommended operating conditions (unless otherwise noted), (fs = 48 khz) parameter test conditions min typ max unit snr (eiaj) a-weighted 93 db dynamic range a-weighted, -60 db, f = 1 khz, 20 hz?20 khz 94 db thd+n 0 db, 1 khz, 20 hz?20 khz 0.09% 5.4 switching characteristics 5.4.1 command sequence timing 5.4.1.1 reset timing?reset control signal parameters over recommended operating conditions (unless otherwise noted) parameter test conditions min typ max unit t w(reset) pulses duration, reset active 50 ns t p(valid_low) propagation delay 1 s t p(valid_high) propagation delay 4 5 ms t d(volume) delay time 42 65 ms t w(reset) t p(valid_high) reset t p(valid_low) t d(volume) valid 1?6 volume 1?6 figure 5?1. reset timing
specifications 39 sles068a?february 2003?revised january 2004 TAS5026A 5.4.1.2 power-down timing?pdn 5.4.1.2.1 long recovery control signal parameters over recommended operating conditions (unless otherwise noted) parameter test conditions min typ max unit t w(pdn) pulse duration, pdn active 50 ns t d(r pdnr) reset high to pdn rising edge 16 mclks ns t p(valid_low) 1 s t p(valid_high) 85 100 ms t d(volume) 42 65 ms reset t p(valid_low) valid 1?6 volume 1?6 pdn normal operation t d(r pdnr) t w(pdn) t p(valid_high) t d(volume) normal operation figure 5?2. power-down and power-up timing?reset preceding pdn
specifications 40 sles068a?february 2003?revised january 2004 TAS5026A 5.4.1.2.2 short recovery control signal parameters over recommended operating conditions (unless otherwise noted) parameter test conditions min typ max unit t w(pdn) pulse duration, pdn active 50 ns t d(r pdnr) pdn high to reset rising edge 16 mclks ns t p(valid_low) 1 s t p(valid_high) 4 5 ms t d(volume) 42 65 ms reset t p(valid_low) valid 1?6 volume 1?6 pdn normal operation t w(pdn) t p(valid_high) t d(volume) normal operation t d(r pdnr) figure 5?3. power-down and power-up timing?reset following pdn 5.4.1.3 error recovery timing?err_rcvry control signal parameters over recommended operating conditions (unless otherwise noted) parameter test conditions min typ max unit t w(er) pulse duration, err_rcvry active 5 mclks ns t p(valid_low) selectable for minimum or maximum 6 47 s t p(valid_high) 4 5 ms
specifications 41 sles068a?february 2003?revised january 2004 TAS5026A err_rcvry t p(valid_low) valid 1?6 t w(er) t p(valid_high) normal operation normal operation figure 5?4. error recovery timing 5.4.1.4 mute timing?mute control signal parameters over recommended operating conditions (unless otherwise noted) parameter test conditions min typ max unit t w(mute) pulse duration, pdn active 3 mclks ns t d(vol) 42 ms t d(vol) volume mute normal operation valid 1?6 normal operation t d(vol) t w(mute) figure 5?5. mute timing
specifications 42 sles068a?february 2003?revised january 2004 TAS5026A 5.4.2 serial audio port 5.4.2.1 serial audio ports slave mode over recommended operating conditions (unless otherwise noted) parameter min typ max unit f (sclk) frequency, sclk 12.288 mhz t su(sdin) sdin setup time before sclk rising edge 20 ns t h(sdin) sdin hold time before sclk rising edge 10 ns f (lrclk) lrclk frequency 32 48 192 khz mclk_in duty cycle 50% sclk duty cycle 50% lrclk duty cycle 50% t su(lrclk) lrclk setup time before sclk rising edge 20 ns mclk high and low time 20 ns 5.4.2.2 serial audio ports master mode, load conditions 50 pf over recommended operating conditions (unless otherwise noted) parameter min typ max unit t (msd) mclk_in to sclk 0 5 ns t (mlrd) mclk_in to lrclk 0 5 ns 5.4.2.3 dsp serial interface mode over recommended operating conditions (unless otherwise noted) parameter min typ max unit f (sclk) sclk frequency 12.288 mhz t d(fs) delay time, sclk rising to fs ns t w(fshigh ) pulse duration, sync 1/(64 fs) ns t su(sdin) sdin and lrclk setup time before sclk falling edge 20 ns t h(sdin) sdin and lrclk hold time from sclk falling edge 10 ns sclk duty cycle 50% t h(sdin) t su(sdin) sclk sdin figure 5?6. right-justified, i 2 s, left-justified serial-protocol timing
specifications 43 sles068a?february 2003?revised january 2004 TAS5026A t su(lrclk) sclk lrclk note: serial data is sampled with the rising edge of sclk (setup time = 20 ns and hold time = 10 ns). figure 5?7. right, left, and i 2 s serial-mode timing requirement lrclk sclk mclk t (mrld) t (msd) figure 5?8. serial audio ports master-mode timing lrclk sclk sdin t su(lrclk) t h(sdin) t h(lrclk) t w(fshigh) t su(sdin) figure 5?9. dsp serial-port timing
specifications 44 sles068a?february 2003?revised january 2004 TAS5026A 64 sclks sclk lrclk sdin 32 bits unused t w(fshigh) 16 bits left channel 16 bits right channel figure 5?10. dsp serial-port expanded timing sclk sdin t su(sdin) = 20 ns t h(sdin) = 10 ns figure 5?11. dsp absolute timing
specifications 45 sles068a?february 2003?revised january 2004 TAS5026A 5.4.3 serial control port?i 2 c operation 5.4.3.1 timing characteristics for i 2 c interface signals over recommended operating conditions (unless otherwise noted) parameter test conditions standard mode fast mode unit parameter test conditions min max min max unit f scl frequency, scl 0 100 0 400 khz t w(h) pulse duration, scl high 4 0.6 s t w(l) pulse duration, scl low 4.7 1.3 s t r rise time, scl and sda 1000 300 ns t f fall time, scl and sda 300 300 ns t su1 setup time, sda to scl 250 100 ns t h1 hold time, scl to sda 0 0 ns t (buf) bus free time between stop and start condition 4.7 1.3 s t su2 setup time, scl to start condition 4.7 0.6 s t h2 hold time, start condition to scl 4 0.6 s t su3 setup time, scl to stop condition 4 0.6 s c l load capacitance for each bus line 400 400 pf sclk sda t h1 t w(l) t f t r t su t w(h) figure 5?12. scl and sda timing sclk sda t h2 t (buf) t su2 t su3 start condition stop condition figure 5?13. start and stop conditions timing
specifications 46 sles068a?february 2003?revised january 2004 TAS5026A
application information 47 sles068a?february 2003?revised january 2004 TAS5026A 6 application information pwm ch. output control avdd_pll avss_pll vrega_cap vregb_cap vregc_cap dvdd_rcl dvss_rcl dvdd_pwm dvss_pwm power supply pll_flt_1 pll_flt_2 sclk lrclk mclkout sdin1 sdin2 sdin3 mclk_in xtal_out xtal_in sda scl cso pwm_ap_1 valid_1 pwm_ap_2 valid_2 pwm ap_3 valid_3 pwm_ap_4 valid_4 pwm_ap_5 valid_5 pwm_ap_6 valid_6 pwm am_3 pwm_am_1 pwm_am_2 pwm_am_4 pwm_am_5 pwm_am_6 clock, pll and serial data i/f pdn reset mute clip err_rcvry serial control i/f reset, pwr dwn and status auto mute de-emphasis soft volume error recovery soft mute clip detect signal processing pwm section pwm ch. pwm ch. pwm ch. pwm ch. pwm ch. pwap pwbm pwam pwbp reset shutdown tas5110 h-bridge m_s clkout aclkx alkx1 alkx0 afsx alkx2 p1.5/ia1/tdi p1.0 p1.3 p1.1 p2.0 p1.4/smclk/tck p1.2 pwap pwbm pwam pwbp reset shutdown tas5110 h-bridge pwap pwbm pwam pwbp reset shutdown tas5110 h-bridge pwap pwbm pwam pwbp reset shutdown tas5110 h-bridge pwap pwbm pwam pwbp reset shutdown tas5110 h-bridge pwap pwbm pwam pwbp reset shutdown tas5110 h-bridge dm_sel1 dm_sel2 dbspd da610 dsp msp430 figure 6?1. typical TAS5026A application
application information 48 sles068a?february 2003?revised january 2004 TAS5026A 6.1 serial audio interface clock master and slave interface configuration 6.1.1 slave configuration TAS5026A (slave mode) sdin1 sdin2 sdin3 xtali xtalo da610 dsp (master mode) clkout afsx aclkr alkx0 alkx1 alkx2 aclkx afsr clkin alkr0 pcm1800 adc sysclk lrck dout bck left analog right analog alkr1 alkr2 other digital audio sources lrck sclk mclko 12.288 mhz xtal osci osco gnd nc mclko figure 6?2. TAS5026A serial audio port?slave-mode connection diagram 6.1.2 master configuration TAS5026A (master mode) sdin1 sdin2 sdin3 xtali xtalo da610 dsp clkout afsx aclkr alkx0 alkx1 alkx2 aclkx afsr clkin alkr0 pcm1800 adc sysclk lrck dout bck left analog right analog alkr1 alkr2 other digital audio sources lrck sclk mclko 12.288 mhz xtal gnd mclko figure 6?3. TAS5026A serial audio port?master-mode connection diagram
mechanical data 49 sles068a?february 2003?revised january 2004 TAS5026A 7 mechanical data pag (s-pqfp-g64) plastic quad flatpack 0,13 nom 0,25 0,45 0,75 seating plane 0,05 min 4040282 / c 11/96 gage plane 33 0,17 0,27 16 48 1 7,50 typ 49 64 sq 9,80 1,05 0,95 11,80 12,20 1,20 max 10,20 sq 17 32 0,08 0,50 m 0,08 0 ? 7 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026
mechanical data 50 sles068a?february 2003?revised january 2004 TAS5026A
appendix a?volume table 51 sles068a?february 2003?revised january 2004 TAS5026A appendix a?volume table volume setting register volume (bin) gain db d7 ? d0 249 1111 1001 24 248 1111 1000 23.5 247 1111 0111 23 246 1111 0110 22.5 245 1111 0101 22 244 1111 0100 21.5 243 1111 0011 21 242 1111 0010 20.5 241 1111 0001 20 240 1111 0000 19.5 239 1110 1111 19 238 1110 1110 18.5 237 1110 1101 18 236 1110 1100 17.5 235 1110 1011 170 234 1110 1010 16.5 233 1110 1001 16 232 1110 1000 15.5 231 1110 0111 15 230 1110 0110 14.5 229 1110 0101 14 228 1110 0100 13.5 227 1110 0011 13 226 1110 0010 12.5 225 1110 0001 12 224 1110 0000 11.5 223 1101 1111 11 222 1101 1110 10.5 221 1101 1101 10 220 1101 1100 9.5 219 1101 1011 9 218 1101 1010 8.5 217 1101 1001 8 216 1101 1000 7.5 215 1101 0111 7 214 1101 0110 6.5 213 1101 0101 6 212 1101 0100 5.5 211 1101 0011 5 210 1101 0010 4.5 209 1101 0001 4 208 1101 0000 3.5 207 1100 1111 3 206 1100 1110 2.5 volume setting register volume (bin) gain db d7 ? d0 205 1100 1101 2 204 1100 1100 1.5 203 1100 1011 1 202 1100 1010 0.5 201 1100 1001 0 200 1100 1000 ?0.5 199 1100 0111 ?1 198 1100 0110 ?1.5 197 1100 0101 ?2 196 1100 0100 ?2.5 195 1100 0011 ?3 194 1100 0010 ?3.5 193 1100 0001 ?4 192 1100 0000 ?4.5 191 1011 1111 ?5 190 1011 1110 ?5.5 189 1011 1101 ?6 188 1011 1100 ?6.5 187 1011 1011 ?7 186 1011 1010 ?7.5 185 1011 1001 ?8 184 1011 1000 ?8.5 183 1011 0111 ?9 182 1011 0110 ?9.5 181 1011 0101 ?10 180 1011 0100 ?10.5 179 1011 0011 ?11 178 1011 0010 ?11.5 177 1011 0001 ?12 176 1011 0000 ?12.5 175 1010 1111 ?13 174 1010 1110 ?13.5 173 1010 1101 ?14 172 1010 1100 ?14.5 171 1010 1011 ?15 170 1010 1010 ?15.5 169 1010 1001 ?16 168 1010 1000 ?16.5 167 1010 0111 ?17 166 1010 0110 ?17.5 165 1010 0101 ?18 164 1010 0100 ?18.5 163 1010 0011 ?19 162 1010 0010 ?19.5
appendix a?volume table 52 sles068a?february 2003?revised january 2004 TAS5026A volume setting register volume (bin) gain db d7 ? d0 161 1010 0001 ?20 160 1010 0000 ?20.5 159 1001 1111 ?21 158 1001 1110 ?21.5 157 1001 1101 ?22 156 1001 1100 ?22.5 155 1001 1011 ?23 154 1001 1010 ?23.5 153 1001 1001 ?24 152 1001 1000 ?24.5 151 1001 0111 ?25 150 1001 0110 ?25.5 149 1001 0101 ?26 148 1001 0100 ?26.5 147 1001 0011 ?27 146 1001 0010 ?27.5 145 1001 0001 ?28 144 1001 0000 ?28.5 143 1000 1111 ?29 142 1000 1110 ?29.5 141 1000 1101 ?30 140 1000 1100 ?30.5 139 1000 1011 ?31 138 1000 1010 ?31.5 137 1000 1001 ?32 136 1000 1000 ?32.5 135 1000 0111 ?33 134 1000 0110 ?33.5 133 1000 0101 ?34 132 1000 0100 ?34.5 131 1000 0011 ?35 130 1000 0010 ?35.5 129 1000 0001 ?36 128 1000 0000 ?36.5 127 0111 1111 ?37 126 0111 1110 ?37.5 125 0111 1101 ?38 124 0111 1100 ?38.5 123 0111 1011 ?39 122 0111 1010 ?39.5 121 0111 1001 ?40 120 0111 1000 ?40.5 119 0111 0111 ?41 118 0111 0110 ?41.5 117 0111 0101 ?42 volume setting register volume (bin) gain db d7 ? d0 116 0111 0100 ?42.5 115 0111 0011 ?43 114 0111 0010 ?43.5 113 0111 0001 ?44 112 0111 0000 ?44.5 111 0110 1111 ?45 110 0110 1110 ?45.5 109 0110 1101 ?46 108 0110 1100 ?46.5 107 0110 1011 ?47 106 0110 1010 ?47.5 105 0110 1001 ?48 104 0110 1000 ?48.5 103 0110 0111 ?49 102 0110 0110 ?49.5 101 0110 0101 ?50 100 0110 0100 ?50.5 99 0110 0011 ?51 98 0110 0010 ?51.5 97 0110 0001 ?52 96 0110 0000 ?52.5 95 0101 1111 ?53 94 0101 1110 ?53.5 93 0101 1101 ?54 92 0101 1100 ?54.5 91 0101 1011 ?55 90 0101 1010 ?55.5 89 0101 1001 ?56 88 0101 1000 ?56.5 87 0101 0111 ?57 86 0101 0110 ?57.5 85 0101 0101 ?58 84 0101 0100 ?58.5 83 0101 0011 ?59 82 0101 0010 ?59.5 81 0101 0001 ?60 80 0101 0000 ?60.5 79 0100 1111 ?61 78 0100 1110 ?61.5 77 0100 1101 ?62 76 0100 1100 ?62.5 75 0100 1011 ?63 74 0100 1010 ?63.5 73 0100 1001 ?64 72 0100 1000 ?64.5
appendix a?volume table 53 sles068a?february 2003?revised january 2004 TAS5026A volume setting register volume (bin) gain db d7 ? d0 71 0100 0111 ?65 70 0100 0110 ?65.5 69 0100 0101 ?66 68 0100 0100 ?66.5 67 0100 0011 ?67 66 0100 0010 ?67.5 65 0100 0001 ?68 64 0100 0000 ?68.5 63 0011 1111 ?69 62 0011 1110 ?69.5 61 0011 1101 ?70 60 0011 1100 ?70.5 59 0011 1011 ?71 58 0011 1010 ?71.5 57 0011 1001 ?72 56 0011 1000 ?72.5 55 0011 0111 ?73 54 0011 0110 ?73.5 53 0011 0101 ?74 52 0011 0100 ?74.5 51 0011 0011 ?75 50 0011 0010 ?75.5 49 0011 0001 ?76 48 0011 0000 ?76.6 47 0010 1111 ?77 46 0010 1110 ?77.5 45 0010 1101 ?78 44 0010 1100 ?78.5 43 0010 1011 ?79 42 0010 1010 ?79.6 41 0010 1001 ?80.1 40 0010 1000 ?80.6 39 0010 0111 ?81.1 38 0010 0110 ?81.5 37 0010 0101 ?82.1 volume setting register volume (bin) gain db d7 ? d0 36 0010 0100 ?82.6 35 0010 0011 ?83 34 0010 0010 ?83.5 33 0010 0001 ?84 32 0010 0000 ?84.6 31 0001 1111 ?85.1 30 0001 1110 ?85.8 29 0001 1101 ?86.1 28 0001 1100 ?86.8 27 0001 1011 ?87.2 26 0001 1010 ?87.5 25 0001 1001 ?88.4 24 0001 1000 ?88.8 23 0001 0111 ?89.3 22 0001 0110 ?89.8 21 0001 0101 ?90.3 20 0001 0100 ?90.9 19 0001 0011 ?91.5 18 0001 0010 ?92.1 17 0001 0001 ?92.8 16 0001 0000 ?93.6 15 0000 1111 ?94.4 14 0000 1110 ?95.3 13 0000 1101 ?96.3 12 0000 1100 ?97.5 11 0000 1011 ?98.8 10 0000 1010 ?100.4 9 0000 1001 ?102.4 8 0000 1000 ?104.9 7 0000 0111 ?108.4 6 0000 0110 ?114.4 5 0000 0101 mute 4 0000 0100 mute 3 0000 0011 mute 2 0000 0010 mute 1 0000 0001 mute 0 0000 0000 mute
appendix a?volume table 54 sles068a?february 2003?revised january 2004 TAS5026A
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) TAS5026Apag active tqfp pag 64 160 green (rohs & no sb/br) cu nipdau level-4-260c-72 hr TAS5026Apagr active tqfp pag 64 1500 none cu nipdau level-2-235c-1 year TAS5026Apagrg4 active tqfp pag 64 1500 green (rohs & no sb/br) cu nipdau level-4-260c-72 hr (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - may not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. none: not yet available lead (pb-free). pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. green (rohs & no sb/br): ti defines "green" to mean "pb-free" and in addition, uses package materials that do not contain halogens, including bromine (br) or antimony (sb) above 0.1% of total product weight. (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedecindustry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 11-feb-2005 addendum-page 1
mechanical data mtqf006a january 1995 revised december 1996 1 post office box 655303 ? dallas, texas 75265 pag (s-pqfp-g64) plastic quad flatpack 0,13 nom 0,25 0,45 0,75 seating plane 0,05 min 4040282 / c 11/96 gage plane 33 0,17 0,27 16 48 1 7,50 typ 49 64 sq 9,80 1,05 0,95 11,80 12,20 1,20 max 10,20 sq 17 32 0,08 0,50 m 0,08 0 7 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026

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